RFD 284 Loading the Host Operating System

Advanced Micro Devices. Company.

Basic Input/Output System. Archaic name for firmware, commonly used in AMD documentation. Note that Oxide systems do not use a "BIOS" in the traditional sense.

A table in flash that describes where code and data required to boot (e.g., the BIOS) are located. Abbreviated "BHD". For example, the BHD points to the BIOS reset vector, so that the PSP may load it into RAM once DRAM has been trained and arrange for the BSC to begin execution in it. Ref [amdpsp].

See "BIOS Directory Table". Ref [amdpsp]

BootStrap Core. The first CPU core brought online when the x86 cores come out of reset. Executes the reset vector code. Responsible for loading and starting the host operating system and ultimately bringing the other CPUs online. Ref <[amd64]>

Cache Disable. Bit in %cr0. If the CD bit is set, caching is disabled on that logical processor. Ref [sdm] and [amd64]

A portmanteau of "cp" and "in and out": CoPy In and Out. A Unix file archiver program, and also the name of archiver’s file format as in, "CPIO files" or "a CPIO archive".

Control Register. Architecturally defined by x86 to control various aspects of the CPU’s operation. Control registers used by phbl include %cr0, %cr4 and %cr3.

Direction flag. Bit in %FLAGS. If clear, string operations increment their source and destination registers; if set, source and destination are automatically decremented.

Dynamic Random Access Memory. Readable and writeable memory where each bit is built from a single transistor and a capacitor. Capacitor leakage currents require each bit to be periodically refreshed, and "DRAM timing training" or just "DRAM training" is the process of determining the refresh interval. DRAM is somewhat slower, but DRAM is cheaper and denser than SRAM (Static RAM). The vast majority of system RAM is DRAM.

Extended Feature Enable Register. An architecturally defined MSR that controls extended features, such as 64-bit mode and the validity of the NX bit in page table entries.

Embedded Firmware Structure (called the "Embedded Firmware Signature" in some AMD documentation; this appears to be an error). A data structure at a fixed address in the "offchip boot storage media" (e.g., flash) that "contains data required to boot the system." E.g., it points to the BIOS reset vector (phbl) and so forth.

Executable and Linkable Format. The object file format used by the host kernel image.

An architecturally defined x86 register that holds both flags resulting from arithmetic operations (for instance, a Z bit indicating that a recent arithmetic operation yielded a zero result, or that two values compared equal), as well as control operations (for instance, whether interrupt delivery is enabled on the CPU).

Global Descriptor Table. An architecturally defined, RAM-resident table of entries describing "segments". Required for 32-bit and 64-mode processor modes.

Global Descriptor Table Register. A hardware register containing a base linear address and bound that point to the GDT.

Gibibyte. A power of two (2^30) as opposed to gigabyte, which is a power of ten (10^9).

Interrupt Flag. A bit in the %FLAGS register indicating whether interrupt delivery is enabled on the CPU. If set, interrupt delivery is enabled; if clear, interrupt delivery is disabled.

Interrupt Descriptor Table. An architecturally defined, RAM-resident table of entries describing how to handle interrupts and exceptions. Indexed by interrupt/exception vector number.

Interrupt Descriptor Table Register. A hardware register that contains a base linear address and bound that point to the IDT.

Kibibyte. A power of 2 (2^10) as opposed to kilobyte, which is a power of ten (10^3).

Long Mode Enable. A bit in the EFER MSR. Puts the CPU into ia32e mode, allowing it to make a long-jump to 64-bit mode.

Mibibyte. A power of 2 (2^20) as opposed to megabyte, which is a power of ten (10^6).

Memory-Mapped IO. Regions of address space that map device registers and are used for IO, as distinct from programmed IO.

Memory Management Unit. A per-CPU hardware device that uses RAM-based tables to relocate and map virtual addresses to physical addresses.

Model-specific register. A register in an integer-indexed namespace that provides programmatic access to a variety of system functions.

Memory Type Range Register(s). A set of MSRs that describes the "memory type" of regions in the physical address space.

Host Operating System. The helios image that manages the physical hardware.

Protection Enable. Bit in %cr0. When set, the CPU is in 32- or 64-bit "protected mode" and memory references are made with respect to the segment descriptors in the GDT.

Paging. Bit in %cr0. When set, paging is enabled and memory accesses on the logical processor are mediated by the page tables configured in the MMU.

Pico Host Boot Loader. The software component in the Oxide architecture that is run from the reset vector and that loads and starts the host operating system.

Page Map Level 4. An architecturally defined level in the page table hierarchy. The root of the page table radix tree when using 4-level paging. The physical address of a valid PML4 must be in %cr3 for paging to work properly.

Platform Security Processor. An AMD-specific "secure execution context" embedded in the x86 SoC. Contains an ARM-based microprocessor on-die that is responsible for DRAM training, loading the reset vector from flash, etc.

Not Write-through. Bit in %cr0. When set along with CD, memory cache-coherency is not maintained.

Non-executable; sometimes "not-executable". A bit in a PTE that prevents the CPU from executing instructions on the page that the PTE maps.

Physical Address Extension. Bit in %cr4.

Page Table Entry. An architecturally defined, word-sized data structure in the paging radix tree. Note that architecture documentation describes a specific meaning to the term, "PTE": this is an entry at the 4th level of the tree that maps a 4KiB page. We tend to use the term more generically and use the specific term, "leaf PTE" when referring to a leaf entry in the tree.

Root of Trust

Architecturally defined x86 registers that are related to the segmented memory model. The segment registers phbl uses are %CS (code segment), %DS (data segment), %ES (extended segment, used by string operations), and %SS (stack segment). In 16-bit mode, these are unchanged from their reset values. In 32-bit mode, these become indices into the GDT, and %CS points to a 32-bit code segment while %DS, %ES and %SS point to a 32-bit data segment covering the first 4GiB of the physical address space. In 64-bit mode, %CS points to a 64-bit code segment while the rest are cleared. Architecturally there exist two more: %FS and %GS. These are unused and ignored in phbl.

System on a Chip.

Service Processor

Universal Asynchronous Receiver/Transmitter. A hardware device for asynchronous serial communication.

Write Protection. Bit in %cr0. When set, the CPU honors page-level write protection bits in PTEs in kernel mode. When cleared, page-level read/write permissions are ignored in kernel mode.